Mechanical stresses within a semiconductor device substrate can modulate device performance. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the NFETs and/or PFETs.
It is known, for example, to provide a patterned and oxidized silicon liner in isolation regions, or spacers on gate sidewalls, to selectively induce the appropriate strain in the channels of the FET devices. By providing patterned oxidized spacers, the appropriate stress is applied closer to the device than the stress applied as a result of the trench isolation fill technique.
While these methods provide structures applying stresses to the devices, they may require additional materials and/or more complex processing, and thus, result in higher cost. In addition, in the methods described above, for example, the stresses in the channel are relatively moderate, which provide only moderate benefit in device performance.
Further, nitride stress liners have been used to improve device performance with enhanced carrier mobility in the channel. The strain induced in the channel by the liner, e.g., nitride, is sensitive to the distance between stress liner and the gate, which is separated by a spacer. However, in an effort to arrange the nitride close to the gate, the spacer is removed.
Further, it is known in the art to utilize two spacers, e.g., a first oxide spacer and a second nitride spacer, and to remove only the second nitride spacer. However, this still disadvantageously results in an oxide spacer of 10-20 nm remaining between the gate and nitride liner. Moreover, another thin oxide layer is below the nitride cover layer which can relax the strain in the channel.